ST STM32F2 User Manual page 1049

UM1940
LL_RCC_RTC_HSE_DIV_26
LL_RCC_RTC_HSE_DIV_27
LL_RCC_RTC_HSE_DIV_28
LL_RCC_RTC_HSE_DIV_29
LL_RCC_RTC_HSE_DIV_30
LL_RCC_RTC_HSE_DIV_31
AHB prescaler
LL_RCC_SYSCLK_DIV_1
LL_RCC_SYSCLK_DIV_2
LL_RCC_SYSCLK_DIV_4
LL_RCC_SYSCLK_DIV_8
LL_RCC_SYSCLK_DIV_16
LL_RCC_SYSCLK_DIV_64
LL_RCC_SYSCLK_DIV_128
LL_RCC_SYSCLK_DIV_256
LL_RCC_SYSCLK_DIV_512
System clock switch
LL_RCC_SYS_CLKSOURCE_HSI
LL_RCC_SYS_CLKSOURCE_HSE
LL_RCC_SYS_CLKSOURCE_PLL
System clock switch status
LL_RCC_SYS_CLKSOURCE_STATUS_HSI
LL_RCC_SYS_CLKSOURCE_STATUS_HSE
LL_RCC_SYS_CLKSOURCE_STATUS_PLL
Calculate frequencies
__LL_RCC_CALC_PLLCLK_FREQ
HSE clock divided by 26
HSE clock divided by 27
HSE clock divided by 28
HSE clock divided by 29
HSE clock divided by 30
HSE clock divided by 31
SYSCLK not divided
SYSCLK divided by 2
SYSCLK divided by 4
SYSCLK divided by 8
SYSCLK divided by 16
SYSCLK divided by 64
SYSCLK divided by 128
SYSCLK divided by 256
SYSCLK divided by 512
HSI selection as system clock
HSE selection as system clock
PLL selection as system clock
HSI used as system clock
HSE used as system clock
PLL used as system clock
Description:
Helper macro to calculate the PLLCLK
frequency on system domain.
Parameters:
__INPUTFREQ__: PLL Input frequency
(based on HSE/HSI)
__PLLM__: This parameter can be one of
the following values:
DocID028236 Rev 2
LL RCC Generic Driver
LL_RCC_PLLM_DIV_2
LL_RCC_PLLM_DIV_3
LL_RCC_PLLM_DIV_4
LL_RCC_PLLM_DIV_5
LL_RCC_PLLM_DIV_6
LL_RCC_PLLM_DIV_7
LL_RCC_PLLM_DIV_8
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