UM1940
DMA Burst Length
LL_TIM_DMABURST_LENGTH_1TRANSFER
LL_TIM_DMABURST_LENGTH_2TRANSFERS
LL_TIM_DMABURST_LENGTH_3TRANSFERS
LL_TIM_DMABURST_LENGTH_4TRANSFERS
LL_TIM_DMABURST_LENGTH_5TRANSFERS
LL_TIM_DMABURST_LENGTH_6TRANSFERS
LL_TIM_DMABURST_LENGTH_7TRANSFERS
LL_TIM_DMABURST_LENGTH_8TRANSFERS
LL_TIM_DMABURST_LENGTH_9TRANSFERS
LL_TIM_DMABURST_LENGTH_10TRANSFERS
LL_TIM_DMABURST_LENGTH_11TRANSFERS
LL_TIM_DMABURST_LENGTH_12TRANSFERS
LL_TIM_DMABURST_LENGTH_13TRANSFERS
LL_TIM_DMABURST_LENGTH_14TRANSFERS
LL_TIM_DMABURST_LENGTH_15TRANSFERS
LL_TIM_DMABURST_LENGTH_16TRANSFERS
LL_TIM_DMABURST_LENGTH_17TRANSFERS
LL_TIM_DMABURST_LENGTH_18TRANSFERS
Encoder Mode
LL_TIM_ENCODERMODE_X2_TI1
LL_TIM_ENCODERMODE_X2_TI2
LL_TIM_ENCODERMODE_X4_TI12
Encoder mode 1 - Counter counts up/down on
TI2FP2 edge depending on TI1FP1 level
Encoder mode 2 - Counter counts up/down on
TI1FP1 edge depending on TI2FP2 level
Encoder mode 3 - Counter counts up/down on both
TI1FP1 and TI2FP2 edges depending on the level
DocID028236 Rev 2
LL TIM Generic Driver
Transfer is done to 1 register starting
from the DMA burst base address
Transfer is done to 2 registers starting
from the DMA burst base address
Transfer is done to 3 registers starting
from the DMA burst base address
Transfer is done to 4 registers starting
from the DMA burst base address
Transfer is done to 5 registers starting
from the DMA burst base address
Transfer is done to 6 registers starting
from the DMA burst base address
Transfer is done to 7 registers starting
from the DMA burst base address
Transfer is done to 1 registers starting
from the DMA burst base address
Transfer is done to 9 registers starting
from the DMA burst base address
Transfer is done to 10 registers starting
from the DMA burst base address
Transfer is done to 11 registers starting
from the DMA burst base address
Transfer is done to 12 registers starting
from the DMA burst base address
Transfer is done to 13 registers starting
from the DMA burst base address
Transfer is done to 14 registers starting
from the DMA burst base address
Transfer is done to 15 registers starting
from the DMA burst base address
Transfer is done to 16 registers starting
from the DMA burst base address
Transfer is done to 17 registers starting
from the DMA burst base address
Transfer is done to 18 registers starting
from the DMA burst base address
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