ST STM32F2 User Manual page 1051

UM1940
__LL_RCC_CALC_PLLCLK_48M_FREQ
__PLLN__: Between 192 and 432
__PLLP__: This parameter can be one of
the following values:
Return value:
PLL: clock frequency (in Hz)
Notes:
ex: __LL_RCC_CALC_PLLCLK_FREQ
(HSE_VALUE,LL_RCC_PLL_GetDivider
(), LL_RCC_PLL_GetN (),
LL_RCC_PLL_GetP ());
Description:
Helper macro to calculate the PLLCLK
frequency used on 48M domain.
Parameters:
__INPUTFREQ__: PLL Input frequency
(based on HSE/HSI)
__PLLM__: This parameter can be one of
the following values:
DocID028236 Rev 2
LL RCC Generic Driver
LL_RCC_PLLM_DIV_61
LL_RCC_PLLM_DIV_62
LL_RCC_PLLM_DIV_63
LL_RCC_PLLP_DIV_2
LL_RCC_PLLP_DIV_4
LL_RCC_PLLP_DIV_6
LL_RCC_PLLP_DIV_8
LL_RCC_PLLM_DIV_2
LL_RCC_PLLM_DIV_3
LL_RCC_PLLM_DIV_4
LL_RCC_PLLM_DIV_5
LL_RCC_PLLM_DIV_6
LL_RCC_PLLM_DIV_7
LL_RCC_PLLM_DIV_8
LL_RCC_PLLM_DIV_9
LL_RCC_PLLM_DIV_10
LL_RCC_PLLM_DIV_11
LL_RCC_PLLM_DIV_12
LL_RCC_PLLM_DIV_13
LL_RCC_PLLM_DIV_14
LL_RCC_PLLM_DIV_15
LL_RCC_PLLM_DIV_16
LL_RCC_PLLM_DIV_17
LL_RCC_PLLM_DIV_18
LL_RCC_PLLM_DIV_19
LL_RCC_PLLM_DIV_20
LL_RCC_PLLM_DIV_21
LL_RCC_PLLM_DIV_22
LL_RCC_PLLM_DIV_23
LL_RCC_PLLM_DIV_24
LL_RCC_PLLM_DIV_25
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