ST STM32F2 User Manual page 1232

LL TIM Generic Driver
LL_TIM_COUNTERMODE_CENTER_UP_DOWN
DMA Burst Base Address
LL_TIM_DMABURST_BASEADDR_CR1
LL_TIM_DMABURST_BASEADDR_CR2
LL_TIM_DMABURST_BASEADDR_SMCR
LL_TIM_DMABURST_BASEADDR_DIER
LL_TIM_DMABURST_BASEADDR_SR
LL_TIM_DMABURST_BASEADDR_EGR
LL_TIM_DMABURST_BASEADDR_CCMR1
LL_TIM_DMABURST_BASEADDR_CCMR2
LL_TIM_DMABURST_BASEADDR_CCER
LL_TIM_DMABURST_BASEADDR_CNT
LL_TIM_DMABURST_BASEADDR_PSC
LL_TIM_DMABURST_BASEADDR_ARR
LL_TIM_DMABURST_BASEADDR_RCR
LL_TIM_DMABURST_BASEADDR_CCR1
LL_TIM_DMABURST_BASEADDR_CCR2
LL_TIM_DMABURST_BASEADDR_CCR3
LL_TIM_DMABURST_BASEADDR_CCR4
LL_TIM_DMABURST_BASEADDR_BDTR
LL_TIM_DMABURST_BASEADDR_OR
1232/1371
TIMx_CR1 register is the DMA base
address for DMA burst
TIMx_CR2 register is the DMA base
address for DMA burst
TIMx_SMCR register is the DMA base
address for DMA burst
TIMx_DIER register is the DMA base
address for DMA burst
TIMx_SR register is the DMA base address
for DMA burst
TIMx_EGR register is the DMA base
address for DMA burst
TIMx_CCMR1 register is the DMA base
address for DMA burst
TIMx_CCMR2 register is the DMA base
address for DMA burst
TIMx_CCER register is the DMA base
address for DMA burst
TIMx_CNT register is the DMA base
address for DMA burst
TIMx_PSC register is the DMA base
address for DMA burst
TIMx_ARR register is the DMA base
address for DMA burst
TIMx_RCR register is the DMA base
address for DMA burst
TIMx_CCR1 register is the DMA base
address for DMA burst
TIMx_CCR2 register is the DMA base
address for DMA burst
TIMx_CCR3 register is the DMA base
address for DMA burst
TIMx_CCR4 register is the DMA base
address for DMA burst
TIMx_BDTR register is the DMA base
address for DMA burst
DocID028236 Rev 2
when the counter is counting up
The counter counts up and down
alternatively. Output compare interrupt
flags of output channels are set only
when the counter is counting up or
down.
UM1940