Ll_Tim_Isenableddmareq_Update; Ll_Tim_Enabledmareq_Cc1; Ll_Tim_Disabledmareq_Cc1; Ll_Tim_Isenableddmareq_Cc1 - ST STM32F2 User Manual

LL TIM Generic Driver
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LL_TIM_IsEnabledDMAReq_UPDATE

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LL API cross
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LL_TIM_EnableDMAReq_CC1

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LL_TIM_DisableDMAReq_CC1

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LL_TIM_IsEnabledDMAReq_CC1

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Function description
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Reference Manual to
LL API cross
1220/1371
__STATIC_INLINE uint32_t
LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef * TIMx)
Indicates whether the update DMA request (UDE) is enabled.
TIMx: Timer instance
State: of bit (1 or 0).
DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1
(TIM_TypeDef * TIMx)
Enable capture/compare 1 DMA request (CC1DE).
TIMx: Timer instance
None:
DIER CC1DE LL_TIM_EnableDMAReq_CC1
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1
(TIM_TypeDef * TIMx)
Disable capture/compare 1 DMA request (CC1DE).
TIMx: Timer instance
None:
DIER CC1DE LL_TIM_DisableDMAReq_CC1
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1
(TIM_TypeDef * TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is
enabled.
TIMx: Timer instance
State: of bit (1 or 0).
DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
DocID028236 Rev 2
UM1940