ST STM32F2 User Manual page 1289

UM1940
LL_USART_SR_RXNE
LL_USART_SR_TC
LL_USART_SR_TXE
LL_USART_SR_LBD
LL_USART_SR_CTS
Hardware Control
LL_USART_HWCONTROL_NONE
LL_USART_HWCONTROL_RTS
LL_USART_HWCONTROL_CTS
LL_USART_HWCONTROL_RTS_CTS
IrDA Power
LL_USART_IRDA_POWER_NORMAL
LL_USART_IRDA_POWER_LOW
IT Defines
LL_USART_CR1_IDLEIE
LL_USART_CR1_RXNEIE
LL_USART_CR1_TCIE
LL_USART_CR1_TXEIE
LL_USART_CR1_PEIE
LL_USART_CR2_LBDIE
LL_USART_CR3_EIE
LL_USART_CR3_CTSIE
Last Clock Pulse
LL_USART_LASTCLKPULSE_NO_OUTPUT
LL_USART_LASTCLKPULSE_OUTPUT
LIN Break Detection Length
LL_USART_LINBREAK_DETECT_10B
LL_USART_LINBREAK_DETECT_11B
Oversampling
LL_USART_OVERSAMPLING_16
LL_USART_OVERSAMPLING_8
Parity Control
LL_USART_PARITY_NONE
LL_USART_PARITY_EVEN
Read data register not empty flag
Transmission complete flag
Transmit data register empty flag
LIN break detection flag
CTS flag
CTS and RTS hardware flow control disabled
RTS output enabled, data is only requested when
there is space in the receive buffer
CTS mode enabled, data is only transmitted
when the nCTS input is asserted (tied to 0)
CTS and RTS hardware flow control enabled
IrDA normal power mode
IrDA low power mode
IDLE interrupt enable
Read data register not empty interrupt enable
Transmission complete interrupt enable
Transmit data register empty interrupt enable
Parity error
LIN break detection interrupt enable
Error interrupt enable
CTS interrupt enable
10-bit break detection method selected
11-bit break detection method selected
Oversampling by 16
Oversampling by 8
Parity control disabled
Parity control enabled and Even Parity is selected
DocID028236 Rev 2
LL USART Generic Driver
The clock pulse of the last data bit is not
output to the SCLK pin
The clock pulse of the last data bit is output
to the SCLK pin
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