ST STM32F2 User Manual page 1290

LL USART Generic Driver
LL_USART_PARITY_ODD
Clock Phase
LL_USART_PHASE_1EDGE
LL_USART_PHASE_2EDGE
Clock Polarity
LL_USART_POLARITY_LOW
LL_USART_POLARITY_HIGH
Stop Bits
LL_USART_STOPBITS_0_5
LL_USART_STOPBITS_1
LL_USART_STOPBITS_1_5
LL_USART_STOPBITS_2
Wakeup
LL_USART_WAKEUP_IDLELINE
LL_USART_WAKEUP_ADDRESSMARK
Exported_Macros_Helper
__LL_USART_DIV_SAMPLING8_100
__LL_USART_DIVMANT_SAMPLING8
__LL_USART_DIVFRAQ_SAMPLING8
__LL_USART_DIV_SAMPLING8
__LL_USART_DIV_SAMPLING16_100
1290/1371
Parity control enabled and Odd Parity is selected
The first clock transition is the first data capture edge
The second clock transition is the first data capture edge
Steady low value on SCLK pin outside transmission
window
Steady high value on SCLK pin outside transmission
window
0.5 stop bit
1 stop bit
1.5 stop bits
2 stop bits
USART wake up from Mute mode on Idle Line
USART wake up from Mute mode on Address
Mark
Description:
Compute USARTDIV value according to
Peripheral Clock and expected Baud Rate
in 8 bits sampling mode (32 bits value of
USARTDIV is returned)
Parameters:
__PERIPHCLK__: Peripheral Clock
frequency used for USART instance
__BAUDRATE__: Baud rate value to
achieve
Return value:
USARTDIV: value to be used for BRR
register filling in OverSampling_8 case
Description:
Compute USARTDIV value according to
Peripheral Clock and expected Baud Rate
in 16 bits sampling mode (32 bits value of
USARTDIV is returned)
Parameters:
DocID028236 Rev 2
UM1940