ZiLOG Z80 Handbook page 91

the test. In the shift instructions, the carry is set or reset by the state
of the bit shifted out of the operand and this provides a convenient
way of testing and conditionally branching on a carry (1 bit) or no
carry (0 bit). Finally, the carry is set from the high order bit of the
result during multiple-precision adds or subtracts. The first add is
an ADD (without carry) while successive adds of higher-order oper-
ands are ADC types, which add in the carry from the lower-order
result (see Fig. 6-3).
MULTIPLE-PRECISION ADD
MS BYTE LS BYTE
00011100 01110111 + 7, 287 (16 B ITS)
+ 01011111 11111100
+ 24. 572 (16 B ITS)
1 CY 0111011 +31,859(16BITS)
01111100
MULTIPLE-PRECISION SUBTRACT
MS BYTE
LS BYTE
00001010 00001010 +426 (16 BITS)
00100000
00000001 -(+8193) (16 B ITS)
1
00001010
00001010 + 426 (16 BITS)
11011111
11111111 -8193 (16 B ITS)
1 • CY 00001001 -7767 (16 B ITS)
11101010
Fig. 6-3. Carry in multiple -precision operations.
PARITY/OVERFLOW FLAG
The parity/overflow flag (bit-position 2 in the flag register) is a
dual-purpose flag. In the parity case, the flag is set to represent odd
parity or the result of the operation. Odd parity occurs when the
sum of the eight bits of the result is even. In this case, the parity
bit is set. If the sum is odd, the parity bit is reset. (See Fig. 6-4).
When the P/V flag is used to represent overflow, the flag is set if
arithmetic overflow occurs after an arithmetic operation. Arithmetic
overflow will occur if in an add or subtract operation of two numbers
of like signs the sign of the result changes, indicating that the result
is too large to be held in eight (or sixteen) bits. Examples of over-
flow conditions are shown in Fig. 6-5. Table 6-4 lists the instructions
that affect the parity/ overflow flag.
RESULT - 00101011
4 ONE B ITS - EVEN PAR ITY, SET PIV FLAG
RESULT - . 00111110 .
5 ONE BITS - ODD PARITY, RESET PIV FLAG
Fig. 6 -4. P/V flag used as
parity indicator.
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