ZiLOG Z80 Handbook page 30

has a fetch cycle as the first byte of the instruction, the operation
code, is fetched from memory and then decoded. In the Z-80, unlike
the 8080, several instructions have two-byte operation codes and
signal Ml will be low during each of the fetches of one byte.
The RESET signal is an active low input signal that is used as a
master CPU reset. This signal would be brought low immediately
after power up, or at any time when the microcomputer system
was to be reset. When RESET is brought low, the following actions
occur:
1. The interrupt enable flip-flop is disabled, preventing system
interrupts except for NMI (see below).
2. Register I, the Interrupt Vector Register, is set to OOH.
3. Register R, the Refresh Register, is set to OOH.
4. Interrupt mode 0 is set.
5. The address bus goes to a high-impedance state.
6. The data bus goes to a high-impedance state.
7. All output-control signals go to the inactive state.
The WAIT signal is a signal associated with slow memories or
I/O devices. As long as the WAIT signal is low, the CPU will "mark
time," doing nothing, while the external memory or I/O device re-
sponds to a previous memory or I/O request. The WAIT signal en-
ables slow memories or (rarely) slow 1/0 devices to be interfaced
to the Z-80 without buffering.
The HALT signal is an active low output signal that goes low
during the time that a HALT instruction is being executed. A HALT
instruction in a program is typically used for one of two conditions.
Either the program has performed all of its functions and termi-
nated, or a halt has been reached and the program is waiting for an
interrupt to occur. When the CPU is in a halt state, it performs no-
operations instructions (NOP) to ensure proper memory refresh
activity.
INTERRUPT-RELATED SIGNALS
The remainin logic signals are associated with interrupt process-
ing. Signal NMI is a negative-edge triggered input that specifies a
nonmaskable interrupt is to be performed. When this signal is mo-
mentarily brought low, the CPU will recognize this interrupt at the
end of the current instruction. When the CPU recognizes the NMI
interrupt, the following actions occur:
1. The current contents of the program counter PC is saved in the
memory stack.
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