ZiLOG Z80 Handbook page 116

able is the signal to the PIO indicating that the PIO address has been
decoded in an I/O operation. M1 is the CPU machine cycle one
signal. and TM are the Z-80 signals related to any I/O opera-
tion. Three interrupt-control signals provide the interrupt INT, IEI,
and IEO functions discussed in Chapter 7, that is, the eternal inter-
rupt to the CPU and interrupt priority encoding. The clock input
signal, 1, is the clock signal from the Z-80 CPU.
TO CPU
ADDRESS
DECODING
(CHIP
ENABLE)
DO
D1
D2
DATA D3
BUS D4
D5
D6-
D7
CONTROL
LINES
PORT B S A EL
CONT T EL
CHIP
AT-
IORQ
RD-
INT
INTERRUPT
CONTROL ITEI
IEO
Z-80 P I O
F4 A6
^r--
A7
PORT A
110 LINES
A RDY PORT A
4
A s T-B } HANDSHAKE
BO
B1
B2
B3 PORT B
B4 I/O LINES
B5
B6
87
^ B RDY
B STB
1 PORT B
HANDSHAKE
t 1
+5 GND
Fig. 8-6. PIO interface signals.
TO
EXTERNAL
110
DEVICE(S)
Internally, the PIO appears as shown in Fig. 8-7. Each port of the
PIO has a number of registers associated with the port. The main
controlling register is the 2-bit mode control register. It is set by
addressing the PIO port and sending a control word from the CPU
with the format shown in Fig. 8-8. The two most significant bits of
the control word determine the mode as follows:
D7, D6
Mode
00 0 output
01 1 input
10 2 bidirectional
11
3 control
123