ZiLOG Z80 Handbook page 112

MIEQ
MRD CS1 R
RESET
D
-
RD
A15- CS2
A
ADDRESS BUS
15-AO
A9-AO
DO
01
D1
1024X
02
D2
8 ROM
03
D3
04
D4
05
Z-80 D5
06
CPU D6 07
D7 08
Irol
RD
1102
1103
WR
1104
256X4 RAM
IORQ
AO-A7
AO-A7
Ml
RD R/W
CE
MREQ
A15
WR
QUAD
LATCH
CP
D I SABLE
G2
TRI-STATE
BUFFERS
AO-A7
1/01
102
1103
1104
AO-A7
RIW
CE
IROQ
MI
RD
Fig. 8-2 . Z-80 interfacing with RAM and ROM.
256X4 RAM
t- OUTPUTS
TO
1 - EXTERNAL
t-- DEVICE
INPUTS
FROM
EXTERNAL
DEVICE
119