ZiLOG Z80 Handbook page 120

In conjunction with the port interrupt vector address register,
each PIO port has an interrupt control word register of 2 bits and
an interrupt mask register of 8 bits. The interrupt control word reg-
ister holds data relating to the interrupt control word shown in Fig.
8-11. The interrupt control word is transferred to a port by address-
ing the port with an OUT instruction and transferring the control
word. Bit seven of the control word controls the interrupt of the
PIO. If bit seven is a one, the port will generate an interrupt; if
reset, the port will not generate an interrupt. As previously dis-
cussed, the interrupt occurs on the rising edge of the STB signal for
modes 0, 1, and 2. Bits six, five, and four are used only for PIO mode
3. Bit five defines the active state for the port I/O lines; if a 1, the
active state is a high state. Bit six specifies either an AND or OR
function for interrupt operation. If bit six is a 1, all bits must go to
an active set (high or low) before an interrupt is generated. If bit
six is a 0, any bit in the active state will generate an interrupt. The
port lines that are monitored for the AND or OR condition are fur-
ther defined for a mask. If bit four is a 1 after the interrupt control
word has been received by the PIO, then the next word sent to the
PIO must be a control word mask which is loaded into the port in-
terrupt mask register. If a bit position is a 1 in the mask, then the
corresponding line will be used as an active line for interrupt gener-
ation.
7 6 5 4 3 2 1 0
EI 1 M O 1 1 1
MASK-MASK WORD TO FOLLOW
H IGHILOW-DETERM INES
ACTIVE STATE FOR INTERRUPT
ANDIOR FUNCTION FOR
INTERRUPT DETECT
ENABLE INTERRUPT
1 = ENABLE
Fig. 8-11 . P1O interrupt control word.
PIO INITIAL CONDITIONS
The PIO is initialized on a power-up or r11 condition without
RD or IORQ. The latter condition enables a reset without power-
down and without adding additional signals to the PIO for reset.
The initial PIO conditions are as follows:
1. Port interrupt enable flip-flops, output registers, and mask reg-
isters reset
2. Mode 1 selected
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