ZiLOG Z80 Handbook page 111

CPU registers. No memory stack is implemented, as no external
RAM memory is provided and CPU registers cannot perform a stack
function.
Data output is provided by the quad latch. Since this is the only
I/O device in the system, any I/O instruction with any I/O address
will address the latch and latch the contents of data bus lines DO-
D3 when signals IORQ and M1 occur during an I/O cycle. Note
that there is also no decoding of RD or WR and that even a read
I/O instruction will output data to the latch. Output lines A, B, C,
and D interface to the outside world.
The above example is admittedly a limited application of the
Z-80, but it does serve to illustrate the simplest usable configura-
tion of a Z-80 system. Even with this simple system, a program
could be implemented to provide a variety of dedicated functions,
such as:
1. Play music via the output latches
2. Provide simple digital-to-analog outputs (with a few additional
external components)
3. Provide timing functions of almost any duration
4. Provide automatic telephone dialing (with additional external
logic)
INTERFACING ROM AND RAM
A more usable system with ROM (or PROM) and RAM memory
and limited I/O capability is shown in Fig. 8-2. A larger ROM
(1K x 8) is used to provide 1024 bytes of program area. Two 256
x 4 bit high-speed RAMS (no WAITS necessary) are used to pro-
vide 256 bytes of read-write storage of dynamic variables. The RAM
(and all system components) are three-state devices to enable "wire-
ORing" all inputs and outputs to the data bus lines. One RAM reads
and writes the four least significant bits of data from the data bus
D3-D0, while the second RAM is used for D7-D4. A quad latch
is used as before for I/O communication for 4-bit outputs from the
CPU. In addition, four external input lines are sampled by gates GI
through G4.
The memory mapping for this configuration is shown in Fig. 8-3.
The ROM memory area is located in locations OOOOH through 3FFH.
The RAM memory area is located at locations FFOOH through
FFFFH (256 locations). Address lines AlO through A14 are not
used. Whenever address line A15 is a 0, ROM memory is being ad-
dressed, and whenever A15 = 1, RAM memory is being accessed.
The I/O addresses in the Z-80 are separate from memory addresses
(as opposed to a memory-mapping 1/0). As in the previous exam-
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