ZiLOG Z80 Handbook page 210

CHAPTER 15
110 and Interrupt Operations-
110 and CPU Control Groups
The I/•O instructions allow the Z-80 system user to input or output
data a byte at a time under programmed I/O. Compatibility with
the 8080 is provided in the Z-80 IN A, (N) and OUT (N),A instruc-
tions which transfer data by means of the A register only. Data may
be transferred between any general-purpose CPU register and the
1/0 device controller with the IN R, (C) and OUT (C),R instruc-
tions, however. I/O block transfer instructions allow semi-automatic
or automatic transfer of up to 256 bytes of data with an operation
similar to the other block-oriented instructions.
The interrupt actions in the Z-80 are controlled by the interrupt
enable, disable instructions and by the interrupt mode instructions.
Several interrupt modes are possible, depending on system configu-
ration. The maximum interrupt capability of a Z-80 system will han-
dle many levels of interrupts with priority encoding and automatic
vectoring.
A REGISTER I/O INSTRUCTIONS
The IN A, (N) and OUT (N),A 1/0 instructions are downwards
compatible with the equivalent IN and OUT 8080 instructions. Both
instructions are a 2-byte immediate instruction with the first byte
specifying the operation code and the second byte specifying an
8-bit I/O address N from 0 through 255. As described in Chapter 8,
when an IN A, (N) instruction is executed, the I/O port address N
is placed on address lines A7 through A0. The addressed device con-
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