ZiLOG Z80 Handbook page 31

2. The CPU transfers control to memory location 0066H, that is,
instruction execution starts from location 0066H which must
contain an NMI interrupt processing program.
An NMI interrupt of this kind cannot be disabled and will always
be recognized by the CPU at the end of the current instruction cycle.
The exceptions to this are that signal BUSRQ will take precedence
over a NMI signal, and that a continuous WAIT state will prevent
the current instruction from ending and thus prevent the NMI from
being recognized.
The main interrupt request is signal INT, an active low input
signal that is supplied by external devices to cause an interrupt. The
INT signal will be recognized by the CPU at the end of the current
instruction if the interrupt enable flip-flop IFF in the CPU has been
set by the program and if the BUSRQ signal is not active. If these
conditions are met, the CPU accepts the interrupt and acknowledges
the interrupt by sending out an IORQ during the fetch (M1) time
of the next instruction. Since IORQ never occurs during MT for an
I/O instruction, the interrupting device recognizes the IORQ and
M1 condition as an interrupt acknowledge. Further actions taken for
this interrupt are discussed later in this section.
CPU ELECTRICAL SPECIFICATIONS
The electrical specifications for the Z-80 microprocessor chip are
shown in Chart 3-1. All inputs and outputs are TTL compatible
facilitating interfacing. There is only one power-supply voltage, a 5-
volt power supply. The Z-80 microprocessor chip alone requires a
maximum current of 200 milliamps. Unlike the 8080, there is only a
single-phase clock input required, which is also at TTL levels. The
frequency of the clock for the original Z-80 was 2.5 megahertz, how-
ever, faster versions will accept a 4-megahertz clock at this time of
writing. Detailed specifications for other dynamic parameters are
provided in Appendix A.
CPU TIMING
All instruction execution in the Z-80 may be broken down into
a set of basic cycles. There are two kinds of cycles, the most basic
being a clock cycle. or T cycle. If a 4-MHz clock is being used for
the Z-80, each T cycle will be a constant length (period) of 250
nanoseconds as shown in Fig. 3-2. The T cycles are used to control
operations within a larger cycle called the machine cycle, or M
cycle. Every instruction executed within the Z-80 consists of from
one to six machine cycles (with the exception of special block-
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