ZiLOG Z80 Handbook page 20

a positive ( zero or greater ) result, or a negative result . A zero flag
and a sign flag in the flag register may be tested by the program after
the add to determine the nature of the result . Other flags are the
carry flag (C), the carry from the high order bit of the accumulator,
the parity/overflow flag ( P/V), specifying a parity or overflow con-
dition, the half carry flag (H ), which is essentially a bed carry or
borrow from the low order bed digit, and the subtract flag (N), set
for bed subtract operations . The flag register format is shown in Fig.
2-6. The interaction of CPU operations and the flags is discussed in
BIT BIT
7 6 5 4 3 2 1 0
FLAG
I S
Z X H
X
PIV N
REGISTER
L CARRY FLAG
SUBTRACT FLAG
LDUAL PURPOSE PARITY/
OVERFLOW FLAG
I NDETERM I NATE
BCD HALF CARRY FLAG
INDETERMINATE
ZERO FLAG
SIGN FLAG
Fig. 2-6 . Flag register format.
detail in a later chapter in this section. Throughout this book the
term flags, flag reigster, and condition codes will be used inter-
changeably.
SPECIAL-PURPOSE REGISTERS
The remaining CPU registers that are available to the programmer
are the I, R, IX, IY, SP, and PC registers. Two of these registers are
exactly the same as they are in the 8080, the SP, or Stack Pointer, and
PC, or Program Counter. The PC register is a 16-bit register that
holds the location of the current instruction being fetched from mem-
ory. Instructions in the Z-80 are one, two, three, or four bytes long.
If a sequence of eight instructions is being executed, as shown in
Fig. 2-7, the PC will hold the indicated values. Note that the PC
always points to the start of the next instruction, and that the CPU
will automatically increment the PC by one, two, three, or four
depending on the length of the instruction being executed. The PC
is available to the programmer only in the sense that it may be
loaded or stored. No arithmetic or logical operations on the PC are
permitted.
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