ZiLOG Z80 Handbook page 115

RAM SELECT
D7-DO
A15-AO
WR
RFSH
MREQ
rot-1104
A11-A0
RMI
1I01-1104 C
All-AO
RIM
1101-1104 CE
All-AO
RNV
I-A
All-AO
R MI
DYNAMIC
RAM
1
DYNAMIC
RAM
2
DYNAMIC
RAM
3
DYNAMIC
RAM
8
Fig. 8-5 . Dynamic RAM refresh.
Z-80 PIO INTERFACING
The Z-80 PIO (Parallel I/O) is a 40-pin Z-80 compatible device
that provides simple interfacing between the Z-80 and peripheral
devices that accept 8-bit parallel data (see Fig. 8-6). Two 8-bit
I/O ports are provided. They can be programmed for either input
or output transfers. In addition to the two sets of eight bidirectional
data lines (A7 - AO and B7 - BO) there are two sets of two control
lines used for handshaking between the I/O device and the PIO, A
RDY and A STB, discussed later. Data is transferred between the
PIO and the Z-80 CPU by data bus lines D7 - DO. Six control lines
control PIO operations under program control from the Z-80 CPU.
PORT B/A SEL selects port A or B. CONTROL/DATA SEL selects
transfer of either control data or operand data to the PIO. Chip en-
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