ZiLOG Z80 Handbook page 66

11AAH
11ABH
11ACH
11ADH
BLOCK TO 11AEH
BE SEARCHED 11AFH
11BOH
11B1H
11B2H
33H
HL AT START (CPID)
i
HL AT END (CPDD)
4-HL AT END (CPID)
t
HL AT START (CPDD)
AT START
(HL) • 11AAH FOR CPIR 11132H FOR CPDR
(BC) ° 9
(A) ° 33H
CPID ACTIONS
1. READ NEXT BYTE
2. ADD 1 TO HL THESE ACTIONS
3. SUBTRACT 1 FROM BC REPEATED FOUR
4. COMPARE BYTE TO (A) AND SET FLAGS TIMES
5. IFBCj0ANDBYTE {ATOSTEP 1
6. GO ON TO NEXT INSTRUCTION
CPDD ACTIONS
1. READ NEXT BYTE
2. SUBTRACT 1 FROM HL ACTIONS
3. SUBTRACT I FROM BC THESE
REPEATED SIX
4. COMPARE BYTE TO (A) AND SET FLAG R
S RIMES
5. IF BC j 0 AND BYTE I A GO TO STEP I
6. GO ON TO NEXT INSTRUCTION
Fig. 5-9 . CPIR and CPDR instructions.
add permits multiple-precision addition and is discussed in Section
II. Subtracts are analogous to the adds. SUB S subtracts the second
operand from the contents of the A register, while SBC A,S sub-
tracts the second operand and the current state of the carry from
the contents of the A register. The add and subtract instructions are
shown in three addressing mode examples in Fig. 5-10.
There are two additional instructions in this group, the INC S
and DEC S instructions. They increment or decrement the contents
of a CPU register (A, B, C, D, E, H, L) or memory location by one
and set certain condition codes as listed in Table 5-4. As an immedi-
ate instruction makes no sense for this one-operand instruction only
register, register indirect HL, and indexed addressing modes are
permitted as shown in Fig. 5-11.
GENERAL-PURPOSE ARITHMETIC
AND CPU CONTROL GROUP
The instructions in this group are listed in Table 5-5. They are
all implied addressing instructions involving one or no operands.
Two of the instructions involve one operand, CPL and NEG. Both
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