ZiLOG Z80 Handbook page 7

Contents
SECTION I-Z-80 Hardware
CHAPTER 1
INTRODUCTION .
. 11
CHAPTER 2
Z-80 ARCHITECTURE . . . . . . . . . . . . . 15
General-Purpose Registers - Flag Registers - Special-Purpose Regis-
ters-Microcomputer Component Parts
CHAPTER 3
INTERFACE SIGNALS AND TIMING. . . . . . . . . . 26
Address and Data Bus-Bus Control Signals-Memory Signals-In-
put/Output Signals-Other CPU Signals-Interrupt-Related Signals
-CPU Electrical Specifications-CPU Timing-MI Cycle-Memory
Data Read and Write Cycles-I/O Read and Write Cycles-
Bus Request/Acknowledge Cycle-Interrupt Request/Acknowledge
Cycle-Nonmaskable Interrupt Request Cycle-Exit From Halt In-
struction-Memory or I/O Wait States
CHAPTER 4
ADDRESSING MODES . . . . . . . . . . . . . 41
Implied Addressing-Immediate Addressing-Extended Immediate
Addressing-Register Addressing-Register Indirect Addressing-Ex-
tended Addressing-Modified Page Zero Addressing-Relative Ad-
dressing-Indexed Addressing-Bit Addressing
CHAPTER 5
INSTRUCTION SET . . . . . . . . . . . . . . 55
8-Bit Load Group-16-Bit Load Group-Exchange, Block Transfer,
and Search Group-8-Bit Arithmetic and Logical Group-General-
Purpose Arithmetic and CPU Control Group-16-Bit Arithmetic
Group-Rotate and Shift Group-Bit Set, Reset, and Test Group-
Jump Group-Input and Output Group