ZiLOG Z80 Handbook page 42

code bits are set according to the results of the shift. Valid values
for the R field of the instruction are as follows:
R Register Shifted
000 B
001 C
010 D
Oil E
100 H
101 L
111 A
Note that all bit permutations are possible except 1102. If 1102
were to be specified in this instruction, the instruction would become
another kind of addressing mode, Register Indirect Addressing and
would shift an external memory location rather than a CPU register.
Strictly speaking, the seven registers that may be specified result in
seven unique instructions, which could be viewed as seven Implied
Addressing instructions.
The AND R instruction is shown in Fig. 4-8. Here the instruction
is a one-byte instruction (because it was an 8080 one-byte instruc-
BYTE 0
AND R LOGICAL AND OF REG ISTER R AND ACCUMULATOR
1 0 1 0 0 R
Fig. 4-8. Register addressing in AND R instruction.
tion) with the least significant three bits of the byte specifying the
register to be used in the instruction. The coding of the registers is
identical to the coding used in the RL R. AND R takes the contents
of the specified R register (A, B, C, D, E, H, or L), logically
Alms it with the contents of the A register, and puts the result
back into the A register. The condition codes are set on the result
of the Aiming operation. As an example, the instruction shown in
Fig. 4-9 would Alen the contents of the D register with the A reg-
ister contents and put the results in the A register.
AND D
BYTE 0
1 0 1 0 010 1 01
R • CPU REGISTER CODE
101102 - OP CODE
101002 - OP CODE
0102 • CODE FORD REGISTER
Fig. 4-9. Register addressing example.
Instruction groups that utilize this addressing mode would in-
clude the 8-Bit Arithmetic and Logical, 16-Bit Arithmetic, Rotate
and Shift, and Bit Set, Reset, and Test groups.
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