ZiLOG Z80 Handbook page 110

Y
CC
I
RESET
Z -80
CPU
MREQ
RD
AD
Al
A2
A3
A4
A5
A6
A7
A8
DO
D1
D2
D3
D4
D5
D6
D7
IORQ
M1
CS1
CS2
• AO 01
A2 512X8 03
A3 ROM 04
•
a
A4 05
a A5 06
H A6 07
a A7 08
A8
DO A OUTPUTS
D1 B TO
D2 C EXTERNAL
D3 D DEVICE
CP
QUAD
LATCH
Fig. 8-1 . A minimum Z - 80 system.
No WAIT conditions are necessary as the memory will always re-
spond in time for data to be read, even at a 4-MHz clock rate. The
output of the ROM is a three-state output, so that the lines are in
a high-impedance state when the ROM is not being addressed. The
eight output lines connect directly to the Z-80 data bus lines DO-
D7. The output device is a quad latch whose four flip-flops are set
by DO-D3 when an output operation is performed.
When the RESET switch is pressed, the RESET input goes low,
initializes the CPU, and starts program execution at location 0 of the
ROM. The ROM program is accessed by making memory requests
MREQ and RDs, as no memory writes are possible, of course, with
a read-only device. For this particular ROM, bringing both chip-
select (CS) inputs to a logic 0 selects the ROM and gates the con-
tents of the memory location addressed by AO-A8. The program is
addressed by addresses XXXXXXX0000000002 through XXXXXXX-
1111111112 where X may be any address, as address lines A9-A15
are not connected. (For clarity, all memory addresses would prob-
ably be in the range 0-51110.) The program probably requires
some memory storage for variables, and this is provided by the 14
^---a
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