ZiLOG Z80 Handbook page 108

use the configuration shown in Fig. 7-8. As before , the interrupt vec-
tor table is at location F000H and the interrupt vector register has
previously been loaded with F000H. The interrupting devices are
labeled 0, 1, and 2; and they have priority in that order. Interrupt
mode 2 has been previously set. During execution of mainline pro-
gram location 0A82H , device 2 interrupts. Interrupt processing rou-
tine 2000H is entered and the environment is saved as shown. After
enabling interrupts , device number 1 interrupts the interrupt proc-
essing routine for device number 2, jumping to location 3000H.
Finally, device 0 interrupts during the middle of the interrupt proc-
essing routine for device number 1 , causing interrupt 0 processing
routine at 4000H to be entered . This routine is completed by an
RETI and the processing routine at 3000 is reentered. This routine
is then completed and, after the RETI , the processing routine at
1000H is again reentered . Finally, the lowest level processing rou-
tine at 1000H is completed , an RETI executed, and a return mode
to the main- line program at 0A82H . At one time during the se-
quence, three nested interrupts were involved . Assuming that the
environment was properly saved and restored and the interrupts
were disabled at proper times, no problems should have been en-
countered with this scheme, or even a great deal more complex
interrupt structure.
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