Interface Signals And Timing - ZiLOG Z80 Handbook

CHAPTER 3
Interface Signals and Timing
The Z-80 CPU chip is a 40-pin dual in-line package. The pinout
of the chip is illustrated in Fig. 3-1, with the pins logically grouped
according to function, rather than the actual physical representation.
ADDRESS AND DATA BUS
The address bus is represented by signals A15 through AO, where
A15 is the most significant bit of the address bus and A0 is the least
significant bit. A15 through AO are active high and are a tri-state
outp,__eanin that when the address bus is inactive ,..,..
__ut LL^ m its _ outputs
are in a high - impedance state. The address bus lines considered to-
gether represent a 16-bit memory or device address. Since 216 ad-
dresses can be held in 16 bits, external memory of 6553610 or 64K
may be addressed directly by the Z-80 CPU. When I/O devices
are addressed, the least significant eight lines of the address bus,
A7-AO, hold the I/O device address, which may be 0 through 25510.
In addition to memory or I/O device addresses , the least significant
seven lines of the address bus hold the contents of the R, or Memory
Refresh Register, for certain times during execution of each in-
struction.
The data bus , signals D7 through DO, are tri-state active high
signals with D7 representing the most significant bit and DO repre-
senting the last significant bit. The data bus is bidirectional, per-
mitting data to be transferred to CPU registers from external mem-
ory or I/O devices or from CPU registers to external memory or I/O.
BUS CONTROL SIGNALS
Associated with the address bus and data bus are two CPU bus
control signals, the input signal BUSRQ and the output (acknowl-
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