ZiLOG Z80 Handbook page 56

except that an immediate value is stored into a memory location
[LD (HL),N; LD(IX+D),N; or LD (IY+D),N]. None of the con-
dition codes are affected by the load (store).
The last instructions of this group load or store the A register
only with a memory location specified by register pointers BC, DE,
or by an extended (direct) addressing. A is loaded by LD A, (BC) ;
LD A, (DE) ; or LD A, (NN) and stored by LD (BC),A; LD (DE),
A; and LD (NN),A. No condition codes are affected.
Examples of this group are shown in Fig. 5-1 which illustrates the
various addressing modes and instruction types.
LD HL, 1025H
INSTRUCTION
LD HL,1025H
0 0 1 0 0 0 0 1
8 BITS
LD (NNI, IX
INSTRUCTION
MEMORY
5020 H
5021 H
STACK
POINTER
REGISTER
LD INN), IX
1 1 0 1 1 1 0 1
0 0 1 0 0 0 1 0
M
20H
50 H
HIGH ORDER
LOW ORDER
25H
10H
LD SP,HL
CPU H REGISTER
CPU L REGISTER
HIGH ORDER
LOW ORDER
I MEMORY ADDRESS 5020H
8BITS
IX REGISTER
8 BITS
8 BITS
8 BITS
Fig. 5-2. Sixteen-bit load group examples.
16-BIT LOAD GROUP
This group allows any register pair BC, DE, HL, or SP, or the IX
and IY registers to be loaded by an extended immediate instruction
(LD DD,NN; LD IX,NN; or LD IY,NN). See Table 5-2. Here a
16-bit immediate value in the instruction is loaded into the selected
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