ZiLOG Z80 Handbook page 74

CPU registers IX, IY, or SP. Increments and decrements of BC, DE,
HL, SP, IX, or IY can be performed by INC SS, INC IX, INC IY,
DEC SS, DEC IX, or DEC IY. The SS-type instructions increment
or decrement BC, DE, HL, or SP depending on the SS field of the
instruction as shown in Fig. 5-13. The remaining increment and
decrements are all implied addressing types.
Three of the instructions in this group permit adding, adding with
carry, or subtracting with carry. The contents of BC, DE, HL, or
SP can operate on the contents of the HL register with the result
going to the HL register. The condition codes are set as shown in
Table 5-6, and an example of the instructions is shown in Fig. 5-14.
ADD IX,PP and ADD IY,RR permit addition of BC, DE, SP, or the
same index register to IX and IY, respectively. The condition codes
are set as listed in the table, and an example of the instruction is
shown in the figure.
ROTATE AND SHIFT GROUP
The instructions in this group include the 8080 (8008) instruc-
tions that rotated only the A register and new instructions to shift
A, B, C, D, E, H, or L or a memory operand in just about every
possible shift configuration. Table 5-7 shows the rotate and shift
instructions.
RLCA ACTION
(8 BITS)
RLA ACTION
(9 B ITS)
RRCA ACTION
18 8 ITSI
RRA ACTION
(9 B ITS)
Fig. 5-15 . RLCA, RLA, RRCA, RRA instructions.
77