ZiLOG Z80 Handbook page 104

after interrupt acknowledge. At any time during the servicing of
one interrupt, one or more higher-priority interrupts may become
active. When this occurs, the interrupt sequences for the higher-
level interrupts are entered. If the interrupt control flip-flop IFF1 ,
has been properly maintained to prevent interrupts from other de-
vices at critical times, such as saving the environment, there should
be no conflicts in servicing n number of interrupts in nested fashion.
Further examples of prioritizing will be discussed for the mode 3
interrupt sequence.
MASKABLE INTERRUPT MODE 1
The next two interrupt modes, mode 1 and mode 2, are not com-
patible with the Intel 8080. Mode 1 is set by the IM 1 instruction.
The interrupt actions of mode 1 are identical to the nonmaskable
interrupt response, except that the Restart location is location 0038H
rather than 0066H. If mode 1 is set and the maskable interrupts are
enabled, then an interrupt request on INT will cause a Restart to
location 0038H. The contents of the program counter will be saved
in the stack and the interrupt servicing routine at location 0038H
will be entered. The advantage of mode 1, as in the NMI interrupt,
is that no external logic is required to jam the Restart onto the data
bus at the proper time. An external interrupt can be implemented
with only enough logic to bring INT active and recognize the inter-
rupt acknowledge. Of course, only one interrupt level is permitted
in this mode.
MASKABLE INTERRUPT MODE 2
The last and most powerful interrupt mode is interrupt mode 2.
This mode allows up to 128 interrupts from external devices, each
fully vectored to an interrupt location anywhere in memory. Fur-
thermore the peripheral modules in the Zilog family, such as the
Z-80 PIO (parallel 1/0), Z80-SIO (serial 1/0), and Z-80-CTC
(counter-timer circuit) may easily be connected in daisy-chained
fashion to allow for complete prioritizing of all interrupt levels.
Mode 2 is set by an IM 2 instruction. The heart of this interrupt
mode is an interrupt vector table anywhere in memory. In general,
the table is (2 x N) bytes long, where N is the number of interrupts
in the system and the start of the table is pointed to by IIIIIIII-
000000002i where I is the contents of the Interrupt Vector regis-
ter I. For any interrupt, the I register supplies the eight most sig-
nificant bits of the table address while the interrupting device sup-
plies the eight least significant bits of the table address. The table
has up to 128 entries as shown in Fig. 7-5. Each entry is two bytes
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