ZiLOG Z80 Handbook page 29

memory address. Essentially, this is part of a chip enable signal for
external memory to inform external memory to output data for a
memory read or to input data for a memory write. The RD and WR
signals are tri-state active low outputs to external memory indicating
whether the memory operation is to be a read or write. When signal
MREQ goes low, either RD or WR will also be low during a portion
of the machine cycle. When MREQ and RD are both low, an ex-
ternal memory read will be performed. When MREQ and WR are
both low, an external memory write will be performed. Both reads
and writes utilize the address on the address bus and transfer data
along the data bus.
The RFSH signal is not associated with normal memory opera-
tion. It is used only when dynamic memories are used as external
memories. Dynamic memories periodically require a refresh to
maintain the data stored within the memory cell. This is essentially
a memory read operation with the data not being transferred from
the memory. Typical dynamic memories are set up so that a refresh
signal can be input to the memory, along with five or six address line
inputs. To refresh an entire memory, six address line inputs would
require sixty-four separate refreshes (26) with the entire refresh
cycle lasting no longer than 2 milliseconds. When the output signal
RFSH is low and signal TTROEQ is also low, external dynamic memory
will use the contents of the least significant seven bits of the address
bus to implement one of the refresh cycles. RFSH is active at every
instruction fetch, and since the R register is continually being in-
cremented after each fetch, the address lines will continually reflect
a new address for the next refresh cycle. For the above example of
six address line inputs, it will take sixty-four instruction cycles to
refresh dynamic memory or approximately 256 microseconds (.256
milliseconds) at about 4 microseconds per instruction, average.
INPUT/OUTPUT SIGNALS
Signal IORQ is a tri-state, active low output signal used for Input/
Output Requests. When signal IORQ goes low, the least significant
eight bits of the address bus, A7-AO, hold an I/O device address.
Signals RD and WR must then be used to determine whether the
I/O operation is to be an I/O read or write. Signal IORQ is also
used in conjunction with signal M1 for interrupt responses as dis-
cussed below.
OTHER CPU SIGNALS
Signal M1 is an active low output signal that indicates the micro-
processor is in the fetch cycle of the instruction. Every instruction
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