Protocol Violation Trigger - Teledyne Kibra DDR User Manual

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Note:
When an MRS occurs that changes parameters that can effect Timing Violations, there is
often a JEDEC‐specified delay in some number of clocks before that new timing value is
applied. The Timing Violation checking in Kibra cannot adjust to that delay in time
automatically, so it is possible in rare cases for a trigger on this violation to be missed, or for
it to fire erroneously. The software analysis of this situation will correctly identify this
violation, since it can easily incorporate this prescribed delay

Protocol Violation Trigger

The following Protocol Violation Triggers are supported. Hover the mouse over the
options to display a tooltip providing a description of the options.
Figure 2.25: Protocol Violation Trigger Settings
Note:
Hold mouse over fields to display tooltips.
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ACT ‐ "Activate" command in all states except "Idle". An Activate command is

detected to a Bank that was already Activated.
RD/WR ‐ "Read" or "Write" commands in all states except "Active". The "Read or

Write" Command is detected for a Bank that was not Activated.
Invalid Command ‐ Invalid commands. A command is detected before a valid

Clock signal was received.
SRE ‐ "Self Refresh Enter" command in all states except "Idle". Self Refresh Enter

occurred before all banks were Idle.
RDA/WRA ‐ "Read Auto" or "Write Auto" commands in all states except "Active".

The "Read Auto" or "Write Auto" Command is detected for a Bank that was not
Activated.
Adjacent CS assertion ‐ "Chip Select" is asserted for more than one DDR clock

cycle as defined by the timing mode parameter setting.
REF/MRS ‐ "Refresh" or "Mode Register Setting" commands in all states except

"Idle". An MRS Command occurred before all banks were idle.
ZQCL/ZQCS ‐ "ZQ Calibration Long" or "ZQ Calibration Short" commands in all

states except "Idle". A ZQCL or ZQCS command occurred before all banks were
idle.
Parity Error ‐ Parity Error (DDR4 Only): Triggers on the occurrence of a Parity

Error. C/A parity error is determined by calculating parity on command/address
lines and comparing that value with "Parity" signal value. This trigger is only
enabled when user enables "C/A Parity Latency Mode" setting in memory con‐
troller section.
Recording Options Setup
Tooltip
K ibra DDR Protocol Analyzer User Manual