Teledyne Kibra DDR User Manual page 9

Contents
5.1.26 V26 - tCKESR SELF REFRESH ENTRANCE to SELF REFRESH EXIT................................................160
5.1.27 V27 - tACTPDEN ACTIVE to POWER DOWN ENTRY ...........................................................................160
5.1.28 V28 - REFPDEN REFRESH to POWER DOWN ENTRY.........................................................................160
5.1.29 V30 - tPRPDEN PRECHARGE / PRECHARGE ALL to POWER DOWN ENTRY..................................161
5.1.30 V31 - tRDPDEN READ / READ AUTO to POWER DOWN ENTRY ........................................................161
5.1.31 V32 - tWRPDEN WRITE to POWER DOWN ENTRY ..............................................................................161
5.1.32 V33 - tWRAPDEN WRITE AUTO to POWER DOWN ENTRY ................................................................161
5.1.33 V34 - tXP POWER DOWN EXIT to a Valid Command without DLL .....................................................161
5.1.34 V35 - tXPDLL POWER DOWN EXIT to a Valid Command with DLL - DDR3.......................................161
5.1.35 V36 - tCKE Clock Enable minimum pulse width ..................................................................................162
5.1.36 V37 - tPD POWER DOWN ENTRY to POWER DOWN EXIT..................................................................162
5.1.37 V38 - tZQCS SHORT Calibration Sequence to a Valid Command ......................................................162
5.1.38 V39 - tZQOper ZQCL to a Valid Command............................................................................................162
5.1.39 V40 - tZQinit First ZQCL after Reset to a Valid Command ..................................................................162
5.1.40 V41 - tMRD MODE Register Set to Mode Register Set.........................................................................162
5.1.41 V42 - tMOD Mode Register Set Command to a Valid Command ........................................................163
5.1.42 V43 - tXPR First Clock Enable High after Reset to MRS......................................................................163
5.1.43 V44 - CCD-S Read to Read Delay (short) Different bank group, same rank DDR4 ..........................163
5.1.44 V45 - tWTW-DBGWrite to Write Delay (short) Different bank group; same rankDDR4....................163
5.1.45 V46 - tWTR- DBGWrite to Read Delay (short) Different bank group; same rank DDR4...................163
5.1.46 V47 - tRRD-SActivate to Activate Delay (short) Different bank group; same rankDDR4 ................163
5.1.47 V48 - tXS-FAST SRX to a Valid Command with DLL- DDR4................................................................164
5.2 Supplemental Timing Information..................................................................................... 164
5.2.1 tWR WR (write recovery for auto-precharge) .........................................................................................164
Appendix B: China Restriction of Hazardous Substances Table ...................165
Appendix C: How to Contact Teledyne LeCroy................................................167
Index:.................................................................................................................. 169
K ibra DDR Protocol Analyzer User Manual
Teledyne LeCroy
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