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3.9 Row Usage Report............................................................................................................. 144
Defining Target Row(s)..................................................................................................................... 145
Define Analysis Detail Parameters .................................................................................................. 146
Define Report Boundary................................................................................................................... 147
Cyclic Row Usage Report................................................................................................................. 147
3.10 Timing Violation Reanalysis ............................................................................................ 147
Chapter 4: Real Time Statistics .........................................................................149
4.1 Devices Dashboard ............................................................................................................ 149
4.2 Real-Time Statistics View .................................................................................................. 150
4.2.1 Real-Time Statistics Buttons ...................................................................................................................152
4.2.2 RTS Preferences .......................................................................................................................................153
4.2.3 RTS Print....................................................................................................................................................154
Appendix A: Application Note ...........................................................................155
5.1 DDR3 and DDR4 JEDEC Timing Violations Summary .................................................... 155
5.1.1 V01 - tRAS ACTIVATE to PRECHARGE command period (Min)...........................................................155
5.1.2 V02 - tRAS ACTIVATE to PRECHARGE command period (Max) ..........................................................155
5.1.4 V04 - tFAW Four Activate Window ..........................................................................................................156
5.1.5 V05 - tRCDx ACTIVATE to internal read or write delay (same bank) ...................................................156
5.1.6 V06 - tWTP WRITE to PRECHARGE delay ..............................................................................................157
5.1.7 V07 - tRTPx READ to PRECHARGE delay ..............................................................................................157
5.1.8 V08 - tRP PRECHARGE to a Valid Command.........................................................................................157
5.1.9 V09 - tWRA WRA to a Valid Command....................................................................................................157
5.1.10 V10 - t RFC REFRESH to a Valid Command .........................................................................................158
5.1.11 V11 - tREFI REFRESH Interval ...............................................................................................................158
5.1.12 V12 - tRTR READ to READ delay (DDR3 - same rank) (DDR4 - same bank group)...........................158
5.1.13 V13 - tdrRTR READ to READ delay (different rank - same DIMM) ......................................................158
5.1.14 V14 - tddRTR READ to READ delay (different DIMM) ..........................................................................158
5.1.15 V15 - tRTW READ to WRITE delay (same rank)....................................................................................159
5.1.16 V16 - tdrRTW READ to WRITE delay (different rank, same DIMM) .....................................................159
5.1.17 V17 - tddRTW READ to WRITE delay (different DIMM) ........................................................................159
5.1.18 V18 - tWTR WRITE to READ delay ( DDR3 - same rank) (DDR4 - same bank group) .......................159
5.1.19 V19 - tdrWTR WRITE to READ delay (different rank, same DIMM) .....................................................159
5.1.20 V20 - tddWTR WRITE to READ delay (different DIMM) ........................................................................159
5.1.21 V21 - tWTW WRITE to WRITE delay ( DDR3 - same rank) (DDR4 - same bank group) .....................159
5.1.22 V22 - tddWTW WRITE to WRITE delay (different rank, same DIMM) ..................................................160
5.1.23 V23 - tddWTW WRITE to WRITE delay (different DIMM)......................................................................160
5.1.24 V24 - tXS SELF REFRESH EXIT to a Valid Command (without DLL) .................................................160
5.1.25 V25 - tXSDLL SELF REFRESH EXIT to a Valid Command (with DLL) ................................................160
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Kibra DDR Protocol Analyzer User Manual
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