Table of Contents
Advertisement
Teledyne LeCroy
5.1.3
V03 - tRRD ACTIVATE to ACTIVATE command period (DDR3 different bank,
same rank) (DDR4 - same bank group)
The minimum interval between Activate of one Bank and the next Activate in the same
Rank is specified to ensure SDRAM has enough time to activate the first row into the
Sense Amps and settle before the next Row is activated. Also known as the "row‐to‐row
delay" this interval allows the necessary latency to process the pending command. For
DDR4, this measurement is for the Same Bank Group, and is denoted as tRRD‐SBG.
Speed
Page Size
Grade
Min (ns)
1KB
Min (ns)
2KB
5.1.4
V04 - tFAW Four Activate Window
Intended to limit thermal overload, the controller is allowed to Activate four different
Banks with in this time window. Activating a 5th Bank within this time window (30 ‐ 50ns)
will cause a violation. Activating the 5th Bank on the exact expiration time is valid.
Speed Grade
Min (ns)
Min (ns)
5.1.5
V05 - tRCDx ACTIVATE to internal read or write delay (same bank)
The minimum interval between Activate and Internal Read or Write is specified to allow
sense amps time to open the selected row. For systems with Additive Latency, tRCDx =
tRCD[spec] ‐ AL.
Speed
800D
Grade
(5‐5‐5)
Min (ns)
12.5
Speed
1333G
Grade
(8‐8‐8)
Min (ns)
12
156
K ibra DDR Protocol Analyzer User Manual
800
max(4nCK, 10ns)
max(4nCK, 10ns)
Page
800
Size
1KB
40
2KB
50
800E
1066E
(6‐6‐6)
(6‐6‐6)
15
11.25
1333H
1600G
(9‐9‐9)
(8‐8‐8)
13.5
10
DDR3 and DDR4 JEDEC Timing Violations Summary
1066
1333
max(4nCK, 7.5ns)
max(4nCK, 6ns)
max(4nCK, 10ns)
max(4nCK, 7.5ns)
1066
1333
1600
37.5
30
30
50
45
40
1066F
1066G
(7‐7‐7)
(8‐8‐8)
13.125
15
1600H
1600J
(9‐9‐9)
(10‐10‐10)
11.25
12.5
1600
max(4nCK, 6ns)
max(4nCK, 7.5ns)
1333F
(7‐7‐7)
10.5
1600K
(11‐11‐11)
13.75
Advertisement
Table of Contents
