5.1.41 V42 - Tmod Mode Register Set Command To A Valid Command; 5.1.42 V43 - Txpr First Clock Enable High After Reset To Mrs; V44 - Ccd-S Read To Read Delay (Short) Different Bank Group, Same Rank Ddr4; V45 - Twtw-Dbgwrite To Write Delay (Short) Different Bank Group; Same Rankddr4 - Teledyne Kibra DDR User Manual

DDR3 and DDR4 JEDEC Timing Violations Summary

5.1.41 V42 - tMOD Mode Register Set Command to a Valid Command

Defines the interval between Mode Register Set and the next valid command. tMOD
violations can also occur during write leveling. This is calculated as max(12 nCK, 15ns) for
all speed bins.

5.1.42 V43 - tXPR First Clock Enable High after Reset to MRS

Defines the interval after initiating Reset (Clock Enable High) to normal operations. This is
defined as max(5nCK, tRFC(min) + 10ns) for all speed bins.
5.1.43 V44 - CCD-S Read to Read Delay (short) Different bank group, same rank
DDR4
Defined as the minimum interval between a READ command and another READ
command to a different bank group within the same Rank.
Speed
Grade
Min (nCK)
5.1.44 V45 - tWTW-DBGWrite to Write Delay (short) Different bank group; same
rank-DDR4
Defined as the minimum interval between a WRITE command and another WRITE
command to a different bank group within the same Rank. This is calculated as WL (AL +
CWL) + tWPRE + BL/2 + WTW‐S.
5.1.45 V46 - tWTR- DBGWrite to Read Delay (short) Different bank group; same
rank DDR4
Defined as the minimum interval between a WRITE command the next READ command to
a different bank group within the same Rank. This is calculated as WL (AL + CWL) +
tWPRE + BL/2 + WTR‐S
5.1.46 V47 - tRRD-SActivate to Activate Delay (short) Different bank group; same
rank DDR4
Defined as the minimum interval between an ACTIVATE command the next ACTIVATE
command to a different bank group within the same Rank.
Speed Grade
X4 Min (nCK)
X8
X16
K ibra DDR Protocol Analyzer User Manual
1600 1866
4 4
1800 1866
4 4
4 4
5 5
2133 2400
4 TBD
2133 2400 3200
4 4 4
4 4 4
5 6 7
T eledyne LeCroy
3200
TBD
163