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Paradox Detection: DCBST not from Line Owner
Paradox Detection: DCBF not from Line Owner
Paradox Detection: DCBI not from Line Owner
Paradox Detection: DCBT not from Line Owner
DCB Ports Arbitration Test
This test checks the different data flows through the DCB asics.
TLB Mechanism Test
This test is performed by two processors on the same CPU card. It contains one sub-test
called "TLB Invalidate in Multiprocessor environment Test". This test checks the TLB
mechanism. The following hardware parts are also checked by this test:
1. Processors (partially).
2. CCA2 ASICs
3. CCD ASICs.
System I/O Sharing Test
This test is performed by all the processors. It contains one sub-test which checks the
capability of all the processors to simultaneously access the same Standard I/O resources.
Here, it checks the Flash EPROM and NVRAM. It also checks the following hardware parts:
1. DCBs ASICs
2. IONIAN ASICs
3. SSGA ASIC.
The test is launched by the BUMP and performed by all the configured processors. The
BUMP manages the test and reports the global test results.
instruction. This is issued by Processor 0 which is set to Global
Copy Back mode. Caching is inhibited for Processor 1.
Here, Processor 1 is set to Local Copy Back mode. Memory
coherency is enabled for Processor 0. This test verifies the
incoherency introduced by the Local Copy Back. Execution of
DCBST by Processor 1 is not verified.
This test enables the Processor 0 for memory coherency. Processor
1 is set to Local Copy Back mode. The DCBF instruction is run from
Processor 1 and verified.
In this test, the DCBI instruction is run by Processor 1 when it is
uncached. The even processor is set to Global Loop Back mode.
In this test, Processor 0 is made to verify the result of the DCBT
(Data Cache Block Touch) instruction on the Processor 1 cache.
The odd processor cache is inhibited without coherency. Processor
0 is set to Global Copy Back mode, with memory coherency
enabled.
A-21
SystemGuard Test Groups
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