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TPGM3
TPGM1
f
1/2
x
Frequency divider
Fig. 6-7 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode)
6.8
SERIAL INTERFACE
The µ PD75512 is provided with two serial interface channels. Table 4-8 indicates differences between channel
0 and channel 1.
Table 6-2 Differences Between Channel 0 and Channel 1
Serial Transfer Mode, Funciton
Clock Selection
3-Line
Transfer Method
Serial I/O
Transfer Completion
Flag
2-Line Serial I/O
Serial Bus Interface (SBI)
(1)
Serial interface function (Channel 0)
The µ PD75512 is equipped with the following four modes:
• Operation stop mode
• Three-line serial I/O mode
• Two-line serial I/O mode
• SBI mode (serial bus interface mode)
26
Internal bus
MODH
Modulo register H (8)
MODH(8)
Modulo latch (14)
PWM pulse generator
INTTPG
IRQTPG set signal
15
2
(
f
x
Channel 0
4
3
f
/2
, f
/2
, TOUT F/F, external clock
X
X
MSB first/LSB first selectable
Serial transfer completion interrupt
request flag (IRQCSI0)
Usable
MODL
Modulo register L (8)
MODL
(6)
7-2
Selector
TPGM5
= 7.8 ms: f at 4.19MHz)
x
4
f
/2
, f
/2
X
X
MSB first
Serial transfer completion flag (EOT)
µ PD75512
Output buffer
PPO
TPGM7
Channel 1
3
external clock
Unprovided
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