Interface Signals; Drst; Dck; Drst Pin Connection Example - NEC IE-V850E1-CD-NW User Manual

Pcmcia card type on-chip debug emulator

Table of Contents

3.2 Interface Signals

This section describes the interface signals.

This is the reset input signal for the on-chip debug unit. This is a negative logic signal for initializing the debug

control unit asynchronously. Barring a problem arising from the specifications of the target device, pull down this

signal to low level.

Upon detection of V

of the target system following integrated debugger startup by the IE-V850E1-CD-NW, the

DRST signal changes from low level to high level to start the on-chip debug unit of the target device.

The change of the DRST signal from low level to high level also resets the CPU.

When debugging is started by starting up the integrated debugger, CPU reset always occurs.

This is the clock input signal. This signal supplies a 20 MHz clock from the IE-V850E1-CD-NW. The DMS and DDI

signals are sampled in synchronization with the rising edge of the DCK signal in the on-chip debug unit, and the data

DDO signal is output in synchronization with the falling edge of the DCK signal. Barring a problem arising from the

specifications of the target device, pull up this signal to high level.

CHAPTER 3 NOTES ON TARGET SYSTEM DESIGN

Figure 3-2. DRST Pin Connection Example

IE-V850E1-CD-NW

DRST

22 Ω

74LV125A

Figure 3-3. DCK Pin Connection Example