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(2)
LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the
LCD clock and number of time slices.
LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDC0 to 00H.
Symbol
7
6
5
LCDC0
0
0
0
LCDC03
LCDC02
0
0
f
XT
5
0
1
f
/2
X
6
1
0
f
/2
X
7
1
1
f
/2
X
LCDC01
LCDC00
0
0
f
/2
LCD
0
1
f
/2
LCD
1
0
f
/2
LCD
1
1
f
/2
LCD
Note Specify an LCD source clock (f
Cautions 1. Bits 4 to 7 must be set to 0.
2. Before changing the LCDC0 setting, be sure to stop voltage boosting (VAON0 = 0).
3. Set the frame frequency to 128 Hz or lower.
Remarks 1. f
:
Main system clock oscillation frequency
X
2. f
: Subsystem clock oscillation frequency
XT
3. The parenthesized values apply to operation at f
As an example, Table 13-3 lists the frame frequencies used when f
source clock (f
).
LCD
LCD Clock (LCDCL)
Time Slots
3
4
Note This setting is prohibited because it causes the frame frequency to exceed 128 Hz.
CHAPTER 13 LCD CONTROLLER/DRIVER
Figure 13-4. Format of LCD Clock Control Register 0
4
3
2
1
0
LCDC03 LCDC02 LCDC01 LCDC00
LCD source clock (f
(32.768 kHz)
(156.3 kHz)
(78.1 kHz)
(39.1 kHz)
LCD clock (LCDCL) selection
6
7
8
9
) frequency of at least 32 kHz.
LCD
Table 13-3. Frame Frequencies (Hz)
9
f
/2
XT
(64 Hz)
21
16
User's Manual U15331EJ4V1UD
0
Address
After reset
FFB2H
00H
Note
) selection
LCD
= 5.0 MHz or f
= 32.768 kHz.
X
XT
(32.768 kHz) is supplied as the LCD
XT
8
7
f
/2
f
/2
XT
XT
(128 Hz)
(256 Hz)
43
85
32
64
R/W
R/W
6
f
/2
XT
(512 Hz)
Note
171
128
255
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