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(a)
Interrupt enable flag (IE)
This flag controls interrupt request acknowledgement operations of the CPU.
When 0, IE is set to the interrupt disabled status (DI), and interrupt requests other than non-maskable
interrupts are all disabled.
When 1, IE is set to the interrupt enabled status (EI). Interrupt request acknowledgement enable is
controlled by the interrupt mask flag for the corresponding interrupt source.
IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b)
Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c)
Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(d)
Carry flag (CY)
This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
CHAPTER 3 CPU ARCHITECTURE
User's Manual U15331EJ4V1UD
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