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(2)
Subclock oscillation mode register (SCKM)
SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
SCKM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SCKM to 00H.
Figure 5-4. Format of Subclock Oscillation Mode Register
Symbol
7
6
5
SCKM
0
0
0
FRC
0
On-chip feedback resistor used
1
On-chip feedback resistor not used
SCC
0
Operation enabled
1
Operation disabled
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid
point of the supply voltage. When the subclock is not used, the power consumption in STOP mode can be
further reduced by setting FRC = 1.
Caution Bits 2 to 7 must be set to 0.
(3)
Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the
CPU clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSS to 00H.
Symbol
7
6
5
CSS
0
0
CLS CSS0
CLS
0
Operation based on the output of the (divided) main system clock
1
Operation based on the subsystem clock
CSS0
0
(Divided) output from the main system clock oscillator
1
Output from the subsystem clock oscillator
Note Bit 5 is read only.
Caution Bits 0 to 3, 6, and 7 must be set to 0.
CHAPTER 5 CLOCK GENERATOR
4
3
2
1
<0>
0
0
0
FRC
SCC
Feedback resistor selection
Control of subsystem clock oscillator operation
Figure 5-5. Format of Subclock Control Register
4
3
2
1
0
0
0
0
0
CPU clock operation status
Selection of the main system or subsystem clock oscillator
User's Manual U15331EJ4V1UD
Address
After reset
R/W
FFF0H
00H
R/W
Note
Address
After reset
R/W
FFF2H
00H
R/W
Note
99
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