Block Diagram Of Timer 50 - NEC PD789488 User Manual

8-bit timer mode control register 50
TCE50 TEG50
(A)
Bit 7 of TM60
(from Figure 7-3(A))
f
X
3
f /2
X
f /2 7
X
f
XT
(B)
Timer 60 interrupt request signal
(from Figure 7-3(B))
(C)
Carrier clock
(from Figure 7-3(C))
Figure 7-2. Block Diagram of Timer 50
Internal bus
(TMC50)
TCL502 TCL501 TCL500 TMD501 TMD500 TOE50
Decoder
8-bit timer counter 50
Clear
Cascade
PWM mode
connection
mode
(D)
Count operation start signal
from Figure 7-3(D)
(cascade connection)
8-bit compare register 50
(CR50)
Match
OVF
(TM50)
Selector
Timer 60 match signal
from Figure 7-3(E)
(E)
(in cascade connection mode)
P30
PM30
output latch
Timer 50 match signal
(F)
to Figure 7-3(F)
(in cascade connection mode)
INTTM50
S
TO50/TMI60/
IN Q
INTP0/P30
CK
Q
R
Timer 50 match signal
(G)
to Figure 7-3(G)
(in carrier generator mode)