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Mnemonic
Operands
MOVW
rp, #word
AX, saddrp
saddrp, AX
AX, rp
rp, AX
XCHW
AX, rp
ADD
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
ADDC
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
SUB
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
Note Only when rp = BC, DE, or HL.
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
CHAPTER 21 INSTRUCTION SET
Bytes
Clocks
rp ← word
3
6
2
6
AX ← (saddrp)
(saddrp) ← AX
2
8
Note
AX ← rp
1
4
Note
1
4
rp ← AX
Note
AX ↔ rp
1
8
2
4
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
3
6
2
4
A, CY ← A + r
A, CY ← A + (saddr)
2
4
3
8
A, CY ← A + (addr16)
A, CY ← A + (HL)
1
6
A, CY ← A + (HL + byte)
2
6
2
4
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
3
6
2
4
A, CY ← A + r + CY
A, CY ← A + (saddr) + CY
2
4
3
8
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
1
6
2
6
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
2
4
(saddr), CY ← (saddr) − byte
3
6
A, CY ← A − r
2
4
A, CY ← A − (saddr)
2
4
3
8
A, CY ← A − (addr16)
A, CY ← A − (HL)
1
6
2
6
A, CY ← A − (HL + byte)
User's Manual U15331EJ4V1UD
Operation
) selected by the processor clock control
CPU
Flag
Z AC CY
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