Block Diagram Of 10-Bit A/D Converter - NEC PD789488 User Manual

ANI0/P60
ANI1/P61
ANI2/P62
ANI3/P63
ANI4/P64
ANI5/P65
ANI6/P66
ANI7/P67
ADS02
ADS01
Analog input channel
specification register 0
(ADS0)
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCRL0).
(2) A/D conversion result register 0 (ADCRL0)
ADCRL0 is a 16-bit register that holds the result of A/D conversion. The lower 6 bits are fixed to 0. Each
time A/D conversion ends, the conversion result in the successive approximation register is loaded into
ADCRL0. The results are stored in ADCRL0 from the highest bit.
The higher 8 bits of the conversion result are stored in FF15H and the lower 2 bits of the conversion result
are stored in FF14H.
ADCRL0 can be read with a 16-bit memory manipulation instruction.
RESET input sets ADCRL0 to 0000H.
Symbol ADCRL0H (FF15H)
ADCRL0
174
CHAPTER 10 10-BIT A/D CONVERTER
Figure 10-1. Block Diagram of 10-Bit A/D Converter
Sample & hold circuit
Band -gap circuit
ADS00
ADCS0 FR02 FR01
Internal bus
User's Manual U15331EJ4V1UD
Voltage comparator
V
Successive
SS
approximation
register (SAR)
Controller
A/D conversion result
register 0 (ADCRL0)
FR00 ADCE0
A/D converter mode
register 0 (ADML0)
ADCRL0L (FF14H)
0 0 0
0
AV
P-ch
AV
INTAD0
Address After reset
FF14H,
0 0
0000H
FF15H
DD
SS
R/W
R