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Mnemonic
Operands
SUBC
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
AND
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
OR
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
XOR
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
336
CHAPTER 21 INSTRUCTION SET
Bytes
Clocks
A, CY ← A − byte − CY
2
4
3
6
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
2
4
A, CY ← A − (saddr) − CY
2
4
3
8
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
1
6
2
6
A, CY ← A − (HL + byte) − CY
A ← A ∧ byte
2
4
3
6
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
2
4
A ← A ∧ (saddr)
2
4
3
8
A ← A ∧ (addr16)
A ← A ∧ (HL)
1
6
2
6
A ← A ∧ (HL + byte)
A ← A ∨ byte
2
4
(saddr) ← (saddr) ∨ byte
3
6
A ← A ∨ r
2
4
A ← A ∨ (saddr)
2
4
3
8
A ← A ∨ (addr16)
A ← A ∨ (HL)
1
6
2
6
A ← A ∨ (HL + byte)
A ← A V byte
2
4
3
6
(saddr) ← (saddr) V byte
A ← A V r
2
4
A ← A V (saddr)
2
4
A ← A V (addr16)
3
8
A ← A V (HL)
1
6
2
6
A ← A V (HL + byte)
User's Manual U15331EJ4V1UD
Operation
) selected by the processor clock control
CPU
Flag
Z AC CY
x
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x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
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x
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x
x
x
x
x
x
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x
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