Releasing Halt Mode By Reset Input; Operation After Releasing Halt Mode - NEC PD789488 User Manual

(c) Release by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started.
RESET
signal
Operation
mode
Clock
Remark f : Main system clock oscillation frequency
X
Releasing Source
Maskable interrupt request
Non-maskable interrupt request
RESET input
x: don't care
Caution Some constraints apply when the flash version (
mode with the subclock multiplied by 4 as the CPU clock. For details, refer to 19.2 Cautions on
µ
PD78F9488 and 78F9489.
CHAPTER 17 STANDBY FUNCTION
Figure 17-3. Releasing HALT Mode by RESET Input
HALT
instruction
HALT mode
Oscillation
Table 17-2. Operation After Releasing HALT Mode
MKxx
0
0
1
−
-−-
User's Manual U15331EJ4V1UD
Wait
15
(2 /f : 6.55 ms)
X
Oscillation
stabilization
Reset
period wait status
Oscillation
stops
Oscillation
IE
0 Executes next address instruction
1 Executes interrupt servicing
x Retains HALT mode
x Executes interrupt servicing
− Reset processing
µ
PD78F9488 and 78F9489) is used in the HALT
Operation
mode
Operation
311