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8-bit timer mode control
register 61 (TMC61)
TCE61 TCL612 TCL611 TCL610 TMD611 TMD610 TOE610
f
X
4
f
/2
X
f
TMI
TMI61/TO61
/INTP2/P32
f
/2
TMI
f
/2
2
TMI
f
/2
3
TMI
Figure 7-4. Block Diagram of Timer 61
Internal bus
8-bit H width compare
register 61 (CRH61)
Decoder
Match
8-bit timer counter 61
(TM61)
Clear
PPG mode
8-bit compare
register 61 (CR61)
output latch
Selector
F/F
Reset
P32
PM32
TO61/TMI61
/INTP2/P32
INTTM61
To timer 20 count clock
input signal in Figure 6-1
Timer 61 interrupt request signal
(in 24-bit event counter mode)
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