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LCD clock control
LCD display mode
register 0 (LCDC0)
register 0 (LCDM0)
LCDC03 LCDC02 LCDC01 LCDC00
2
2
5
f
/2
X
f
6
f
/2
LCD
X
Prescaler
7
f
/2
X
f
f
f
f
f
XT
LCD
LCD
LCD
LCD
6
7
8
2
2
2
2
VAON0
Clock
generator for
boosting
Booster circuit
CAPH CAPL
V
V
LC2
LC1
Figure 13-2. LCD Controller/Driver Block Diagram
LCDON0
VAON0
LIPS0
LCDM00
9
LCD
LCDCL
clock
selector
Segment voltage
controller
Common voltage
controller
V
LC0
Internal bus
LCD voltage boost
Display data memory
control register 0 (LCDVA0)
FA00H
GAIN
7
6 5
4
3 2 1 0
Timing
controller
3 2 1 0
Selector
LCDON0
Segment
Common driver
driver
COM0 COM1 COM2 COM3
S0
FA0FH
FA10H
.........
7
6 5
4
3 2 1 0
7
6 5
4
3 2 1 0
........
3 2 1 0
3 2 1 0
........
Selector
Selector
LCDON0
LCDON0
........
........
........
........
Segment
Segment
........
driver
driver
. . . . . . . . .
S15
S16
Selected by mask option
or port function register
FA1BH
.......
7
6 5
4
3 2 1 0
........
3 2 1 0
........
Selector
LCDON0
........
........
........
........
Segment
........
driver
. . . . . . . . .
S27
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