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(4)
Subclock selection register (SSCK) (
This register is used to control the operation of the ×4 subsystem clock multiplication circuit.
SSCK is set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Caution This register is valid only in the
µ
PD789488 and 789489 will simply make it invalid, causing no operational effect.
Symbol
7
6
SSCK
0
0
SCT
0
Operation stopped (subsystem clock source (32.768 kHz) supplied to the CPU)
1
Operation enabled (clock that is the subsystem clock multiplied by 8 (262 kHz) supplied to the CPU)
Note The register is set to 00H only by RESET input.
Cautions
1. Always set bits 1 to 7 to 0.
2. Write to the SCT flag prior to setting the CSS0 flag to 1 following the release of reset. Write
operations following the first operation are invalid (input the RESET signal to rewrite).
100
CHAPTER 5 CLOCK GENERATOR
µ
PD78F9488, 78F9489 only)
µ
Figure 5-6. Subclock Selection Register Format
5
4
3
0
0
0
Control of ×4 subsystem clock multiplication circuit
User's Manual U15331EJ4V1UD
PD78F9488 and 78F9489; however, writing to it in the
2
1
0
0
0
SCT
Address
After reset
R/W
Not
FF46H
Retained
R/W
e
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