Multiplier Operation - NEC PD789488 User Manual

14.4 Multiplier Operation

The multiplier of the µPD789489 Subseries can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 14-3
shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H.
<1> Counting is started by setting MULST0.
<2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value
is incremented by one.
<3> If MULST0 is cleared when the counter value is 111B, the operation is stopped. At this time, MUL0 holds the
data.
<4> While MULST0 is low, the counter and slave are cleared.
Figure 14-3. Multiplier Operation Timing (Example of AAH × D3H)
CPU clock
MRA0
MRB0
MULST0
Counter
Selector output
MUL0
(Master)
(Slave)
270
CHAPTER 14 MULTIPLIER
AA
D3
000B 001B
00AA 0154
00AA
0000
00AA
User's Manual U15331EJ4V1UD
010B 011B 100B 101B
0000 0000 0AA0 0000
01FE 01FE 01FE 0C9E 0C9E
01FE 01FE 01FE 0C9E
110B 111B 000B
2A80 5500 00AA
371E 8C1E
0C9E 371E 0000