Speed Loop (Asr) Structure - Omron SYSDRIVE 3G3FV User Manual

High-function general-purpose inverter
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Basic Operation

5-5-4 Speed Loop (ASR) Structure

The following block diagram shows the structure of the speed loop.
Frequency
reference
Detected
speed
H Gain Settings
When using "V/f control with PG feedback," set the gain at the minimum frequency and maximum fre-
quency.
Max. Frequency Gain Settings (C5-01 and C5-02)
Set ASR proportional gain 1 (C5-01) and ASR integral time 1 (C5-02) at the maximum frequency.
Parameter
Display
p y
number
name
C5-01
ASR P Gain 1 0.00 to 300.00
C5-02
ASR I Time 1
Note B: Basic or Advanced
---: Not applicable.
Min. Frequency Gain Settings (C5-03 and C5-04)
Set ASR proportional gain 2 (C5-03) and ASR integral time 2 (C5-04) at the minimum frequency.
Parameter
Display
p y
number
name
C5-03
ASR P Gain 2 0.00 to 300.00
C5-04
ASR I Time 2
Note B: Basic or Advanced
---: Not applicable.
The following graph shows how the proportional gain and integral time are calculated from parameters
C5-01 through C5-04.
5-50
Change
limiter
U1-21
Setting range
g
g
Units
Factor
0.000 to 10.000 s
Setting range
g
g
Units
Factor
0.000 to 10.000 s
(Max. frequency)
Limiter
Default
setting
V/f
Control
0.20
---
0.200
---
Default
setting
V/f
Control
0.02
---
0.050
---
Motor speed (Hz)
E1-04
Chapter 5
Output frequency
U1-22
Valid access levels*
V/f with
Open Loop
PG
Vector
B
---
B
---
Valid access levels*
V/f with
Open Loop
PG
Vector
B
---
B
---
Flux
Vector
B
B
Flux
Vector
B
B

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