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2.14.166 Register 4CDh (offset = 4CDh) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
FB_AGC_BAND0_
2-0
LNA_GAIN8[10:8]
2.14.167 Register 4CEh (offset = 4CEh) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
FB_AGC_BAND0_
7-0
LNA_GAIN9[7:0]
2.14.168 Register 4CFh (offset = 4CFh) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit
Field
FB_AGC_BAND0_
2-0
LNA_GAIN9[10:8]
2.14.169 Register 4D0h (offset = 4D0h) [reset = 0h]
7
6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
SBAU337 – May 2020
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Figure 2-2049. Register 4CDh
5
4
Table 2-2063. Register 4CD Field Descriptions
Type
Reset
R/W
0h
Figure 2-2050. Register 4CEh
5
4
FB_AGC_BAND0_LNA_GAIN9[7:0]
R/W-0h
Table 2-2064. Register 4CE Field Descriptions
Type
Reset
R/W
0h
Figure 2-2051. Register 4CFh
5
4
Table 2-2065. Register 4CF Field Descriptions
Type
Reset
R/W
0h
Figure 2-2052. Register 4D0h
5
4
FB_AGC_BAND0_LNA_GAIN10[7:0]
R/W-0h
Copyright © 2020, Texas Instruments Incorporated
3
2
FB_AGC_BAND0_LNA_GAIN8[10:8]
Description
LNA Gain for Band0 for temp index 8 in case of External LNA
Control , Gain for DVGA Index 8 in case of External DVGA
control
3
2
Description
LNA Gain for Band0 for temp index 9 in case of External LNA
Control , Gain for DVGA Index 9 in case of External DVGA
control
3
2
FB_AGC_BAND0_LNA_GAIN9[10:8]
Description
LNA Gain for Band0 for temp index 9 in case of External LNA
Control , Gain for DVGA Index 9 in case of External DVGA
control
3
2
Serial Interface Register Maps
FB Top Register Map
1
0
R/W-0h
1
0
1
0
R/W-0h
1
0
911
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