Texas Instruments AFE79 Series Programming & User Manual page 1156

IO Wrap Register Map
2.16.476 Register 8A5h (offset = 8A5h) [reset = 2h]
7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
OVR_SEL_INTPI_
1-1 ADC_SYNC_N_AB
_1
OVR_INTPI_ADC_
0-0
SYNC_N_AB_1
2.16.477 Register 8A8h (offset = 8A8h) [reset = 0h]
7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
SEL_INTPI_ADC_
2-1
SYNC_N_AB_2
POL_INTPI_ADC_
0-0
SYNC_N_AB_2
2.16.478 Register 8A9h (offset = 8A9h) [reset = 2h]
7 6
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
OVR_SEL_INTPI_
1-1 ADC_SYNC_N_AB
_2
OVR_INTPI_ADC_
0-0
SYNC_N_AB_2
1156
Serial Interface Register Maps
Figure 2-2739. Register 8A5h
5 4
Table 2-2755. Register 8A5 Field Descriptions
Type Reset
R/W 1h
R/W 0h
Figure 2-2740. Register 8A8h
5 4
Table 2-2756. Register 8A8 Field Descriptions
Type Reset
R/W 0h
R/W 0h
Figure 2-2741. Register 8A9h
5 4
Table 2-2757. Register 8A9 Field Descriptions
Type Reset
R/W 1h
R/W 0h
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3 2
OVR_SEL_INT
PI_ADC_SYNC
Description
control to select whether the input function
intpi_adc_sync_n_ab_1 needs to be overriden ot not. 1
indicates override.
override value for ovr_sel_intpi_adc_sync_n_ab_1 is made
high
3 2
SEL_INTPI_ADC_SYNC_N_AB_
2
R/W-0h
Description
select control for intpi_adc_sync_n_ab_2. 0 indicates take
from parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
polarity control for intpi_adc_sync_n_ab_2. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
3 2
OVR_SEL_INT
PI_ADC_SYNC
Description
control to select whether the input function
intpi_adc_sync_n_ab_2 needs to be overriden ot not. 1
indicates override.
override value for ovr_sel_intpi_adc_sync_n_ab_2 is made
high
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1 0
OVR_INTPI_A
DC_SYNC_N_
_N_AB_1 AB_1
R/W-1h R/W-0h
1 0
POL_INTPI_AD
C_SYNC_N_A
B_2
R/W-0h
1 0
OVR_INTPI_A
DC_SYNC_N_
_N_AB_2 AB_2
R/W-1h R/W-0h
SBAU337 – May 2020